Six tiers of suppliers separate quartz sand from a finished chip. This page walks through every tier in plain English, maps the global dependency, then compares it to India's actual 2026 capability.
Every chip passes through these stages in order. Skip any one and the rest becomes impossible. The closer to T0 you go, the more geographic and corporate concentration you find.
A fab doesn't just need wafers. It needs ~50 gases, ~30 photoresists, hundreds of wet-chemical formulations, CMP slurries, sputtering targets, and photomasks — all at parts-per-trillion purity. Each sub-category is its own oligopoly.
Silicon wafers
Shin-Etsu 27%, SUMCO 24% (Japan = 51%), GlobalWafers 17% (Taiwan), Siltronic 12% (Germany), SK Siltron 9% (Korea).
Photoresist
TOK, JSR, Shin-Etsu, Fujifilm, Sumitomo Chemical. EUV resist top-4 = 75%. DuPont (US) is the only non-Japanese player at scale.
Specialty gases
Air Liquide (FR) + Linde (UK) + Taiyo Nippon Sanso (JP). Neon concentration: Ukraine 70% pre-2022; xenon price spiked 10× during the war.
CMP slurries
Entegris/CMC 30%+ (MA), DuPont 22%, Fujimi 15% (Japan), AGC, Resonac. Market $2.4B in 2026.
Wet chemicals
Mitsubishi Chemical + BASF ~25% combined. Stella Chemifa for ultra-pure HF (the 2019 Korea–Japan crisis material). Market: $4.8B → $8.6B by 2032.
Sputtering targets
JX Nippon Mining (JP) leads, Materion (US), Plansee (AT), Mitsui Mining. Every metal layer uses a target — copper, tungsten, cobalt, ruthenium.
Photomasks (merchant)
Photronics (US), Toppan/Tekscend (JP), DNP (JP). The "stencil" fabs print through. Advanced-node EUV masks are usually in-house at TSMC/Samsung/Intel.
Photomask blanks
Near-monopoly on EUV mask blanks — stacks of 40+ molybdenum/silicon layers on ultra-flat quartz. No Hoya/AGC blanks, no EUV masks, no EUV chips.
Rare gases
By-products of Russian/Ukrainian steel mills until 2022. Now diversified across Japan, China, US. Helium from Qatar + Russia + Algeria + US = 90%.
A modern fab has 400–700 process tools in its cleanroom. They cluster into ~12 categories, each dominated by 2–4 firms. One category missing and the whole process line stops.
Lithography — advanced
Only EUV supplier on Earth. $180–380M, 180 tons. Supply chain: Zeiss (optics), Trumpf (40 kW laser), Cymer (light source, ASML-owned).
Lithography — mature
DUV i-line and KrF scanners for 90nm+ nodes. Canon's nanoimprint (NIL) is the long-shot challenger. Legacy install bases across Japan/Korea/China.
Deposition + CMP + implant
US #1 equipment maker ($27B). PVD/CVD/ALD deposition, ion implant, CMP, inspection. Every non-litho step passes through AMAT.
Etch
US $15B etch/deposition specialist. Plasma etch removes unprotected material after lithography to carve circuits into the wafer.
Coat/develop + etch
Japan's $15B equipment champion. TEL coat/develop tools are paired literally side-by-side with every ASML scanner.
Metrology + inspection
US metrology leader ($10B). Every wafer is measured dozens of times. Onto Innovation (MA) and Nova are alternatives.
Diffusion + ALD + furnaces
Japanese batch-thermal-process specialist (Hitachi spinoff). LP-CVD, ALD, oxidation, annealing. Every oxide, nitride, polysilicon gate starts here.
Wafer cleaning
Wafers are cleaned dozens of times during chip fabrication. Screen Holdings (Kyoto) leads single-wafer cleaning.
Ion implant
Shooting dopant atoms (B, P, As) into silicon to make transistors. Axcelis (MA) specializes in power/mature-node; AMAT leads leading-edge.
Test (ATE)
Every finished chip is tested on ATE. Advantest (JP) + Teradyne (MA) + Cohu = 55% share. Market $16B (2026).
Probe cards
Precision arrays of thousands of needles that touch every die on a wafer during test. 3nm+ pushes 10,000+ channels per card. FormFactor dominates leading-edge.
Vacuum + abatement
Every process chamber has vacuum pumps. Ebara (JP) + Edwards (UK, Atlas Copco) duopoly. Abatement burns toxic effluent before it reaches atmosphere.
Once the wafer leaves the fab, it still needs to be diced, mounted on substrates, wire-bonded or flip-chip bumped, encapsulated, tested, and shipped. The back-end has its own oligopolies — especially in substrates.
OSAT — top-3
ASE $18.5B (Taiwan, includes SPIL), Amkor $6.3B (US HQ, Asian fabs), JCET $5B (China, +19% YoY). Market $51B → $77B by 2031.
ABF substrates — top-5
Unimicron 22% (TW), Ibiden (JP), AT&S (AT — only European), Nan Ya PCB (TW), Shinko (JP). Taiwan alone = 45% of world ABF output.
Ceramic substrates
High-power, high-reliability packages for automotive, defense, power electronics. Complements the organic ABF substrate market.
Bonding wire + leadframes
Heraeus (DE), Tanaka Kikinzoku (JP) for gold/copper bonding wire. Mitsui Mining & Smelting, Shinko for lead frames.
Encapsulants
Hitachi Chemical (now Resonac), Sumitomo Bakelite. Mold compounds + underfill that protect the die inside the package.
Fab construction
Exyte (Stuttgart, merged with M+W) — turnkey cleanroom fab builder. Top-5 fab construction firms = 49% of a ~$100B market.
A chip is patterned silicon. To pattern it you need wafers from Japan, photoresist from Kawasaki, lithography from Veldhoven, optics from Oberkochen, lasers from Ditzingen, and gases from France and (until 2022) Ukraine. Every TSMC fab sits at the end of this chain.
TSMC · End-to-end · 2026
Click any marker for a plain-English explainer. Toggle tiers via the top-right control. Animated dashed lines show directional flow — wafers to fabs, fabs to OSAT, OSAT to customers.
T0 + T1 · Materials
Quartz + neon + wafers + photoresist + chemicals + gases. Japanese firms dominate T1: 51% wafers, 88% photoresist.
T2 · Equipment
ASML (EUV monopoly) + Zeiss optics + Trumpf laser + Applied / Lam / KLA (US) + Tokyo Electron. Top-5 = 65% of market.
T3 · TSMC Fabs
Taiwan (7): Hsinchu ×2, Longtan, Taichung, Tainan ×2, Kaohsiung. Overseas (4): Nanjing, Camas WA, Arizona, Kumamoto, Dresden.
T4 · OSAT partners
ASE Technology ($18.5B rev, 45% share), Amkor ($6.3B), JCET ($5B, +19% YoY). Top-3 control half the market.
T5 · Fabless customers
Apple (#1), Nvidia, AMD, Qualcomm, Broadcom, MediaTek. Apple alone buys ~20–25% of TSMC quarterly revenue.
T5 · EDA + IP
EDA: Synopsys 46% + Cadence 35% + Siemens 13% = 94% share. IP: Arm dominant, RISC-V now at 25% penetration.
Two operational facilities, three ramping, one under construction. Ten approved projects totaling ₹1.60 lakh crore under ISM 2.0. Every wafer, every lithography tool, every photoresist currently comes from abroad — the red dashed lines show exactly which routes.
India · As of March 2026
Gujarat cluster (Dholera + Sanand) outlined in blue. Red dashed arrows show import dependencies from Japan, Germany, Netherlands, US, France. Design clusters in Bangalore, Hyderabad, and IIT Madras shown in pink.
T3 · Front-end Fabs
Tata-PSMC Dholera (28-110nm, ₹91,000 cr, first silicon late 2026) + RIR Power SiC (Bhubaneswar, India's first SiC fab, ₹618 cr, epitaxy Mar 2026) + SCL Mohali (legacy 180nm, strategic/ISRO).
T4 · OSAT / ATMP
Micron Sanand (oper.), Kaynes Sanand (oper.), CG Semi Sanand (pilot), Tata Jagiroad (Apr-26 commission), HCL-Foxconn Jewar (2028).
T5 · Design clusters
Bangalore + Hyderabad (Intel 13k, Nvidia 3.8k, AMD $400M, Qualcomm flagship, Arm Noida) + Chennai (IIT Madras, Mindgrove, InCore) + Kerala (Netrasemi) + Noida.
ISM Projects total
2 fabs + 8 OSAT/ATMP approved. ₹1.60 lakh cr ($19B) committed across 6 states. DLI: 24 chip design projects backed.
Operational today
Commercial production: Micron Sanand (Feb-26), Kaynes Sanand (Mar-26). Tata Jagiroad commissioning Apr-26 (3rd).
Upstream imports (T0–T2)
Wafers (Japan), photoresist (Japan), lithography (NL), specialty gases (FR/JP), equipment (US/NL/JP). INOX Air Products (₹500 cr Dholera gas hub, 2026) is the first Indian T1 entrant.
Mapping every Indian-built capability against the six tiers. The further up you go (T0 / T1 / T2), the sparser India's footprint. T4 and T5 are where India's real mass sits today.
T0 · Raw materials
No domestic neon / xenon / krypton / semi-grade quartz production. Imports 100% of electronic specialty gases + rare gases.
T1 · Refined inputs
INOX Air Products Dholera gas hub (₹500 cr, 2026). Linde India in negotiation. Reliance, Aarti, Deepak Nitrite, Navin Fluorine could enter specialty chemicals. No domestic wafers, resist, CMP slurries, or masks yet.
T2 · Equipment
Zero domestic equipment manufacturing. All lithography, deposition, etch, implant, metrology imported from US, NL, Japan.
T3 · Fabs
Tata-PSMC Dholera (28-110nm, Gujarat), RIR Power SiC (Bhubaneswar, Odisha — India's first SiC fab), SCL Mohali (legacy 180nm, ISRO/strategic).
T4 · OSAT + substrates
5 OSATs: Micron, Kaynes, CG Semi (Sanand), Tata Jagiroad, HCL-Foxconn Jewar. Plus Syrma SGS × Shinhyup PCB (Andhra Pradesh, ₹1,800 cr) and Kaynes Circuits.
T5 · Design
Global GCCs: Intel 13k, Nvidia 3.8k, AMD $400M Bangalore, Qualcomm flagship Hyderabad, Arm Noida, NXP 2,500. Indian startups: Mindgrove, InCore, Netrasemi, Saankhya, SignalChip, Calligo.
Twenty-four DLI-approved chip design projects + a wave of Series-A fundraises in 2024–2025 mark the first generation of Indian-founded, India-headquartered fabless companies actually taping out and shipping product.
Mindgrove Technologies
India's first indigenously-designed commercial high-performance MCU. Uses Shakti RISC-V cores. Dec 2024 Series A led by Rocketship.vc + Speciale Invest. DLI: ₹15 cr for Vision SoC.
InCore Semiconductors
RISC-V processor IP solutions spun out of IIT Madras SHAKTI (2018). Concept-to-FPGA in <10 minutes. $3M seed from Peak XV (ex-Sequoia India).
Netrasemi
Edge AI semiconductor startup (founded 2020). Power-efficient NPU + silicon IP portfolio. July 2025 ₹107 cr Series A led by Zoho + Unicorn India Ventures. Validates Kerala as a chip hub.
Saankhya Labs
AI processors for defense and telecom; 5G modems. DLI-approved Feb 2024 for 5G telecom SoC. Part of Tejas Networks (Tata Group acquired 2021).
SignalChip
India's first company to design indigenous 4G LTE and 5G modem chipsets from the ground up. Sovereign cellular modem capability — rare globally.
Calligo Technologies
8-core Posit-enabled RISC-V CPU "TUNGA" unveiled June 2024. Targets HPC, Big Data, AI/ML workloads. India's highest-performance fabless silicon attempt.
Morphing Machines
Many-core processor (REDEFINE) for data analysis, AI, telecom. Incubated at IISc since 2006. Series A within 18 months of seed. Long-horizon deep-tech.
Chipspirit
Services + solutions provider in the semiconductor space (founded 2018). ASIC design services with special focus on turnkey projects. DLI beneficiary.
Mindgrove + InCore at IIT-M Park
Two of the three commercial Shakti-family RISC-V startups are co-located at IIT Madras Research Park — a proof point for the academic-to-commercial pipeline.
Indian chip design startups received approximately ₹380 crore ($45M) in funding in 2024. 24 DLI projects approved by Jan 2026. Biggest milestones: Mindgrove shipping MCU commercially; Netrasemi validating Kerala as a chip hub; Calligo unveiling a Posit RISC-V CPU. Pattern: IIT-M RISC-V lineage, Bangalore/Hyderabad design talent, government DLI + private Series-A layering.
Six Centres of Excellence in Nanoelectronics (CEN) at IIT/IISc, plus the new Bharat Semiconductor Research Centre at IIT Madras + SCL Mohali. $8B committed to research infrastructure over five years.
Bharat Semiconductor Research Centre
Government-backed semiconductor research centre modeled on IMEC (Belgium), ITRI (Taiwan), MIT Microelectronics Lab. Co-located at IIT Madras and SCL Mohali; potential split into a standalone research org.
Investment: ₹66,500 cr ($8B) over 5 years. SCL Mohali separately modernized with $2B. Establishment began 2024.
Research focus: Process R&D, advanced packaging, compound semi, talent pipeline, and pre-competitive IP shared across industry, academia, startups.
Why it matters: India's first attempt at a world-class shared-cleanroom research institution — the institutional missing piece between academic research and commercial fabs.
INUP-i2i · Nanoelectronics network
Indian Nanoelectronics Users' Programme — Idea to Innovation (INUP-i2i). Brings together all six CEN centers under a single umbrella for external researchers + startups.
Research-grade tape-outs, PhD training, industry partnerships. Where many Indian semiconductor PhDs come from.
SCL Mohali
Semi-Conductor Laboratory, Mohali. Under the Department of Space. Legacy 180nm process for ISRO, DRDO, and strategic defense chips. $2B modernization under ISM — being upgraded to at least 45nm.
SCL was established in 1984 — before TSMC. A devastating 1989 fire (₹60 cr in equipment lost, cause unclear) set India back decades. In 2026 it serves as the research-scale silicon pipeline for Shakti RISC-V, satellite payload chips, and strategic electronics.
Design-Linked Incentive
DLI scheme provides up to 50% capex support + 6% net sales incentive over 5 years for approved Indian semiconductor design projects.
24 projects approved as of January 2026 — microprocessors, satellite communication, energy metering, surveillance, IoT SoCs.
72 companies have active EDA tool access through government-subsidized licenses.
DLI + ISM 2.0 together form the "design layer + fab layer" stack that the ecosystem needs.
India produces ~600,000 electronics graduates per year but faces a projected shortfall of 250,000–300,000 semiconductor professionals by 2027. The gap is qualitative, not quantitative — only 5–15% of graduates are industry-ready for fabs/OSATs/design centers.
Projected shortfall by 2027
Critical shortages in process engineering, physical design, analog/RF, verification, and packaging. These are slow-to-train roles — 5–7 years of mentored experience before someone is genuinely productive.
ISM 2.0 talent target
Government target under ISM 2.0, aligned with state-level semiconductor curricula in Gujarat, Karnataka, Tamil Nadu, Telangana. Private training programs filling the gap.
Voices shaping the conversation on India's semiconductor story — journalists, researchers, industry bodies, government. Not exhaustive, but a solid starting point for anyone tracking the space.
Journalist · Expert
IIT-M + UMD alumnus, 10+ years in semi fabrication. India's most consistent semiconductor journalist — Swarajya, Deccan Herald, Gulf News, Moneycontrol. The go-to for deep analysis of ISM.
Think tank · Author
Deputy Director, Takshashila Institution. Chairs High Tech Geopolitics Programme. Co-author of "When the Chips Are Down" and "Missing in Action." Best-in-India on chip geopolitics.
Policy · Research
Carnegie India fellow. Authored "Geopolitics of the Semiconductor Industry and India's Place in It." Former CCI. Sharp on export controls and digital antitrust.
Minister · Govt
Union Minister for Electronics & IT, Railways, I&B. Most active government account on semiconductor policy announcements. Source for ISM 2.0 news, fab inaugurations, foreign JV signings.
ISM · Official
Official ISM account (LinkedIn primarily; X presence growing). Led by CEO Amitesh Kumar Sinha (Additional Secretary, MeitY). Authoritative for approvals, disbursements, and policy updates.
MeitY · Govt
Ministry account. Cross-posts ISM updates, PLI scheme announcements, DLI approvals. Pair with @AshwiniVaishnaw for full official coverage.
Industry body
India's primary semiconductor industry association. Represents domestic + MNC voices. Active on conferences (SEMICON India, VLSI Design), policy advocacy, and workforce programs.
Tata · Manufacturing
Official Tata Electronics account. Updates on Dholera fab construction, Jagiroad OSAT commissioning, Qualcomm partnership. The single most important corporate voice in Indian semi.
Micron · MNC
Micron's corporate X. Active on Sanand ATMP (India's first operational semi facility), DRAM roadmap, and HBM announcements. Follow for MNC-India manufacturing perspective.
SEMI · Global
Global semiconductor industry association. Publishes SEMICON India, World Fab Forecast, equipment shipment data. Best single source for global context on India's fab buildout.
Academia · Research
Home of Shakti RISC-V, InCore Semiconductors, Mindgrove alumni network, Bharat Semiconductor Research Centre (upcoming). Most active academic account on chip design.
Startup · RISC-V
The most prominent Indian fabless startup on X. Updates on commercial MCU ship dates, DLI milestones, RISC-V advocacy. Good signal for where Indian startup ecosystem is heading.
Each card below is one structural gap: what's missing, why it matters, who owns it globally, and realistic paths forward. Written as a briefing memo — read sequentially or jump to a gap.
Silicon wafer manufacturing
A silicon wafer is the disc of ultra-pure crystalline silicon every chip begins as. India imports essentially 100% of semiconductor-grade wafers. To pattern a single chip you first need a wafer polished to atomic flatness — and nobody in India currently makes them at 300mm or the purity the industry requires.
This matters because wafers are the foundation of every other step. The Tata-PSMC fab in Dholera, targeting 50,000 wafers per month of 28nm-to-110nm production by late 2026, will buy every one from Shin-Etsu, SUMCO, GlobalWafers, or Siltronic. That's a permanent supply agreement baked into the fab's economics, not a temporary condition.
The global picture is a textbook oligopoly. Shin-Etsu 27%, SUMCO 24%, GlobalWafers 17%, Siltronic 12%, SK Siltron 9% — top five account for 89% of 300mm wafer revenue.[1] Entering is hard because Czochralski crystal pulling takes decades of experience, capex per plant is $1B+, and the tolerance for atomic-scale flaws is tighter than operating a fab: a wafer with a 10nm particle defect is scrap.
What it would take: a JV with SUMCO, Siltronic, or SK Siltron rather than a greenfield build. Capex $1.5–3B, 500–1,000 specialized engineers (most not yet in India), 5–7 years to qualified output. ISM 2.0 flags wafer manufacturing as priority; one Indian project reportedly targets June 2026 commercial ops* though scale is unclear.
The plausible path is a partnership model — feasible medium-term (2028–2031). Leading-edge (3nm-and-below) wafers are out of reach near-term.
Lithography equipment
Lithography is the step where a circuit pattern is "printed" onto a wafer using light. For everything smaller than 7nm, the required machine is EUV — and exactly one company on Earth makes it: ASML in Veldhoven, Netherlands.
A single EUV scanner costs $180–380 million and weighs 180 tons. It contains mirrors made by Zeiss so precise their imperfections are measured in picometers, and a 40 kW Trumpf laser powerful enough to vaporize tin droplets 50,000 times per second. India has no domestic lithography industry — not for EUV, DUV, or even i-line steppers used at 180nm.
Why uniquely hard? EUV is arguably the most complex machine ever commercialized. ASML took 20+ years and tens of billions — much funded by Intel, Samsung, and TSMC — to productize. China has tried for a decade with SMEE and has not approached DUV immersion, let alone EUV. There is no second source.
For EUV, building indigenous capability is not feasible in any reasonable timeline. For DUV i-line and older nodes, a partnership with Nikon or Canon (both squeezed out of leading-edge by ASML) is plausible on a 7–10 year horizon — enough for sovereign capability at 90nm+ nodes that dominate automotive, power, and industrial chips.
The realistic path: accept lithography as an import dependency, diversify across ASML + Canon + Nikon, and invest in lithography sub-components (precision stages, EUV reticles, inspection tools) where India could contribute as a sub-supplier. Lower-profile but more achievable.
Photoresist & specialty chemicals
Photoresist is the light-sensitive polymer coated onto wafers before each lithography step. When UV light hits, the chemistry changes and a circuit pattern transfers from a mask onto the wafer. It is the photographic film of chip making. Japan owns it.
Approximately 88–90% of the global photoresist market is supplied by five Japanese firms: TOK, JSR, Shin-Etsu, Fujifilm, Sumitomo Chemical.[2] For EUV-grade photoresist, the top four hold 75%. The only non-Japanese player of significance is DuPont (US).
India has zero domestic photoresist production at semiconductor grade. Tata-PSMC Dholera will buy DUV i-line and KrF resist from Japan; any future 7nm fab would need EUV resist — also Japan.
Building requires polymer chemistry expertise (Shin-Etsu's photoresist grew out of 60 years of silicone chemistry) plus obsessive particle control (counts under 10 per liter, purity above 99.9999%). Realistic partners: DuPont, Sumitomo, or Dongjin Semichem. Indian commercial-grade resist is plausible in 2029–2032 with the right JV; nothing sooner is realistic.
The broader specialty chemicals category (CMP slurries, cleaning chemistries, deposition precursors) is dominated by Merck EMD (Germany), Fujifilm, and US firms. This is more accessible — Indian chemical companies (Reliance, UPL, Aarti) have relevant capabilities. An ISM 2.0 push here could yield real supply-chain participation in 2027–2029.
Specialty & rare gases
A modern fab uses 50+ different high-purity gases daily. Most are industrial (nitrogen, argon, oxygen). A handful are rare: neon (DUV lasers), xenon and krypton (etching + EUV source), helium (coolant), exotic etch gases (NF3, SF6).
The 2022 invasion of Ukraine revealed the concentration. Ukraine — primarily Iceblick (Odesa) and Cryoin (Mariupol) — supplied ~70% of the world's neon and ~40% of its krypton.[3] Xenon went from $15/liter in 2020 to $100+/liter by mid-2022. The industry avoided catastrophe by spending ~$3B hedging.
India has near-zero specialty-gas production. Linde India operates at industrial scale, not sub-ppb purity. Micron Sanand and Tata Dholera will source from Air Liquide (France), Linde (global), and Taiyo Nippon Sanso (Japan) — three firms controlling ~80% of the market.
Building is modest compared to wafers or lithography: $50–200M per gas plant, partnership with Linde or Air Liquide (both expanding in India anyway), 2–3 year build. Co-located gas plants at Dholera and Sanand are already being negotiated.
Near-term progress is feasible and underway. Rare gases (neon, xenon) remain a diversification challenge — the answer is multiple sources globally, not building Indian production.
Leading-edge process nodes
India's most advanced announced node is 28nm (Tata-PSMC Dholera). TSMC entered HVM on 2nm in Q4 2025. Between 28nm and 2nm there are seven nodes: 22, 16, 10, 7, 5, 3, 2. India is structurally behind.
This gap matters less than it sounds — for most real-world chips. Automotive silicon, power management, industrial controllers, MEMS, RF, display drivers, analog/mixed-signal products are manufactured at 28nm and older nodes. These account for ~2/3 of all wafer volume globally. Indian fabs at 28nm will have plenty of customers.
The gap matters for AI accelerators, smartphone SoCs, leading-edge GPUs, servers — applications moving aggressively toward 3nm and below, which India is not positioned to serve.
Capex to enter leading-edge is $20B+ per fab at 3nm/2nm, requires EUV (ASML will sell, India is unrestricted), and requires a deep talent pool that doesn't yet exist. TSMC's 2nm fab has 3,000+ process engineers; India has ~50 people with that specific experience. Capex is achievable. Talent is not — at least not in 2026–2030.
A two-phase strategy: near term anchor mature nodes at scale, build 1–2 fabs, dominate automotive and industrial, train 10,000 process engineers. Medium term (2030–2035) push to 14nm or 10nm via foundry partnership (PSMC, UMC, GlobalFoundries). Leading-edge (sub-5nm) is a 2035+ conversation.
EDA tools
EDA software takes a high-level chip description and converts it into the billion-transistor layout a fab can manufacture. Three companies dominate: Synopsys (46%), Cadence (35%), Siemens EDA (13%). 85%+ of all EDA revenue, all US-HQ.[4]
Every Indian chip design — from Qualcomm Bangalore's Snapdragon SoCs to IIT Madras's Shakti RISC-V core — uses these tools. India is one of the largest user bases globally but has no domestic EDA at commercial production quality. Open-source alternatives (OpenROAD, Magic, ngspice, Yosys) are good enough for education and 130nm-up, but fall short at 28nm and below.
The dependency risk has precedent: when the US applied export controls on Huawei in 2019, EDA licenses were included and HiSilicon's advanced-node design operation effectively shut down within months. A similar action against India is unlikely but not impossible.
Easier than hardware because the technology is software — no fabs, no clean rooms. Harder because existing players have 30 years of accumulated process technology files (PDKs) signed with every foundry. Bangalore has enormous Synopsys/Cadence/Siemens engineering presence — the talent exists.
Two-track path: participate aggressively in OpenROAD / CHIPS Alliance (contribute code + PDKs to become structurally important); in parallel, build a domestic EDA player focused on niches (verification, formal methods, physical design for mature nodes). A ₹500–1,000 cr investment over 5–7 years could produce a credible domestic player. Among the highest-leverage gaps to address.
Semiconductor IP
IP cores are pre-designed building blocks — CPUs, GPUs, memory controllers, USB, DDR — that chip designers license rather than designing from scratch. The dominant supplier is Arm (UK, SoftBank-owned), whose cores power essentially every non-Apple smartphone.
This is the one bottleneck where India has real existing strength. IIT Madras's Shakti processor family is a production-grade open-source RISC-V CPU, developed over 10+ years, with silicon taped out on SCL Mohali 180nm. C-DAC's Vega targets a similar niche. The global RISC-V ecosystem — an open, royalty-free ISA — hit 25% processor market penetration by January 2026,[5] with Meta and Qualcomm aggressively adopting it.
This gives India a plausible path to sovereign CPU IP without needing to dethrone Arm. RISC-V is open. An Indian SoC's cores can be Shakti or Vega — built in India, maintained in India, modifiable without licensing costs or geopolitical exposure.
Capitalizing requires: investment in the RISC-V ecosystem (more IITs, more commercial spinouts like InCore and Shakti Semiconductors), integration into ISM 2.0 and DLI schemes, and active engagement with RISC-V International. Capex per startup is small ($10–50M) but cumulative effect is significant. This is the highest-leverage, lowest-cost bottleneck on the list.
Process-engineering talent
India produces ~600,000 electronics graduates per year. The projected semiconductor workforce shortage by 2027 is 250,000–300,000 professionals.[6] These numbers look compatible; they are not.
The gap is qualitative, not quantitative. Of 600k graduates, only 5–15% are industry-ready for semiconductor roles at the depth a modern fab, OSAT, or design center requires. Critical shortages concentrate in process engineering (running a lithography tool, debugging an etch yield problem), physical design (translating circuits into layout), analog and RF, verification, and packaging. 5–7 years of mentored experience before someone is genuinely productive.
Fabs and OSATs ramping now (Tata Dholera, Tata Jagiroad, Kaynes, CG Semi) need tens of thousands of these engineers combined. PSMC and Tata can transfer experienced Taiwanese engineers, but visa and cultural friction are unsustainable at scale. Without domestic talent, fabs struggle with yield — the single largest determinant of fab economics.
Decade-long structural investment in applied semiconductor education. Stanford + MIT + UC Berkeley graduate ~100 semiconductor-focused PhDs per year combined; Taiwan's NTU/NCTU graduate more; India's entire IIT system graduates a fraction. ISM 2.0 targets "1 million chip-ready engineers by 2030." State governments (Gujarat, Karnataka, TN, Telangana) partnering with universities on specialized curricula. Private players (MOSart Labs, KeenSemi, VLSI Expert, Takshila) building parallel pipelines.
Treat talent as infrastructure. A ₹2,000–5,000 cr investment over 10 years in semiconductor-focused institutes (IIT Bombay's Nanoelectronics Center scaled 10x), paired with industry-sponsored internships at every approved facility, is realistic with strong precedent (Taiwan's ITRI, Israel's Talpiot). This is the bottleneck that determines whether India's 2026 fabs produce world-class chips or mediocre ones.
Other gaps worth noting
A photomask is the "stencil" lithography projects through onto the wafer. Photronics, Toppan, and DNP dominate at all nodes; India has near-zero capacity. For mature-node fabs this is addressable (one Indian mask shop could serve multiple domestic fabs); for advanced-node EUV masks it is not — the technology is tied to the fab's own tooling and is typically done in-house at TSMC/Samsung/Intel. A 28–180nm domestic mask shop would be a useful modest-capex investment ($200–500M, 3–5 year build).
When an OSAT packages a chip, the die sits on a substrate — a tiny printed circuit board (organic laminated resin or ceramic) that connects the die to the outside world. Unimicron (Taiwan), Nanya PCB, Ibiden (Japan), Shinko (Japan) dominate. India has zero semiconductor-grade substrate production. With five OSATs in India ramping 2026–2028, this is an immediate supply bottleneck. Lower-risk than wafers or photoresist; credible entry for Indian PCB makers (Kaynes itself, Amara Raja-adjacent players). 3–5 year build, $300–800M capex.
A fab uses 2–5 million gallons of ultrapure water per day — a town of 50,000 people. Dholera has water infrastructure from smart-city plans, but long-term sustainability as multiple fabs scale up is not guaranteed. Primarily a policy/infrastructure challenge, not technology — but a real constraint.
The realistic shape of India's semiconductor sovereignty in 2035 is not an autarky at 2nm. It is a credible domestic T3–T4 presence at mature nodes, growing participation in T1 at the specialty-chemical and gas layer, strong T5 design leveraging RISC-V, and accepted long-term dependencies on Japanese resist, Dutch lithography, and US EDA.
Three priorities
Given India's actual 2026 starting position — two operational OSATs, one fab ramping at 28nm, strong existing design talent, weak upstream supply — the highest-leverage gaps to close first are talent, RISC-V IP, and specialty chemicals and gases.
Talent is foundational: every other gap becomes harder to close without it, and the gap is visible in the productivity of the fabs now coming online. RISC-V IP is uniquely accessible — India's existing strength in Shakti and Vega can be amplified with modest capital to yield genuine sovereign IP within 3–5 years, which no other bottleneck permits on that timescale. Specialty chemicals and gases are reachable via partnership-driven co-location strategies already being negotiated for Dholera and Sanand; the capex per win is small relative to the supply-chain resilience provided.
The hard bottlenecks — wafers, lithography, leading-edge nodes, EDA — are real but slow and expensive. Wafers via partnership is plausible over 5–7 years. Lithography is plausibly never addressable at EUV scale. EDA is addressable at the niche level (verification, mature nodes) but not as a frontal assault on Synopsys/Cadence. Leading-edge nodes will come when the workforce and supply chain sustain them — probably 10+ years out.
That is both less ambitious than the rhetoric suggests and more achievable than any alternative.
* Asterisked numbers are based on press reporting and have not been cross-checked against official filings. Treat with caution.